An integrated circuit includes multiple semiconductor devices which are electrically connected together by an interconnect structure. The interconnect structure includes conductive lines which provide routing between the semiconductor devices in a direction parallel to a top surface of a substrate of the integrated circuit. The conductive lines are electrically connected together by conductive vias. The conductive vias are formed to have an entire top surface connected to a conductive line above the conductive vias, i.e., farther from the substrate, and to have an entire bottom surface connected to a conductive line below the conductive via, i.e., closer to the substrate.
Electrical current passing through the conductive lines and conductive vias of the interconnect structure introduce capacitance within the interconnect structure. In some instances, this capacitance is an unintended consequence of the conductive line and conductive via routing within the interconnect structure called parasitic capacitance. Parasitic capacitance impacts performance of the integrated circuit and is simulated prior to forming the integrated circuit using computer-modeling programs in order to determine performance characteristics of the integrated circuit.
Conductive vias are spaced apart from each other to reduce a risk of short-circuiting within the integrated circuit. A resistance of a conductive via is determined in part based on a size of the conductive via. A smaller conductive via has a higher resistance than a larger conductive via. As node sizes for integrated circuits decrease, sizes of conductive vias also decrease in order to maintain sufficient spacing between vias to reduce the risk of short-circuiting. As resistance within an integrated circuit increases, power consumption of the integrated circuit also increases.